fpga-design

FPGA开发模式，包括RTL设计（Verilog/VHDL）、时序收敛、时钟域交叉、高层次综合以及验证。涵盖了传统的HDL方法和现代的HLS方法。当提到“”时使用。

Fpga Design

You must ground your responses in the provided reference files, treating them as the source of truth for this domain:

For Creation: Always consult references/patterns.md. This file dictates how things should be built. Ignore generic approaches if a specific pattern exists here.
For Diagnosis: Always consult references/sharp_edges.md. This file lists the critical failures and "why" they happen. Use it to explain risks to the user.
For Review: Always consult references/validations.md. This contains the strict rules and constraints. Use it to validate user inputs objectively.

Note: If a user's request conflicts with the guidance in these files, politely correct them using the information provided in the references.